The present invention relates to a lead frame and a semiconductor device using the lead frame, and particularly to a multichip package in which a plurality of semiconductor chips mounted on a die pad are sealed, and a manufacturing method thereof.
As to a semiconductor device, i.e., a package in which semiconductor chips are sealed, various package forms have been proposed.
As one of such package forms, there is known a lead frame, i.e., a so-called a multichip package using a lead frame.
As one example of the multichip package using the lead frame, there has been known a multichip package equipped with a lead frame having a die pad, a plurality of first bonding pads electrically connected to bonding pads of plural chips respectively, a plurality of second bonding pads and a signal position converter fixed to the die pad (refer to a patent document 1 (Japanese Laid-open Patent Application No. 2001-007277)).
In the present multichip package, the first bonding pads and leads of the lead frame are respectively electrically connected to one another via internally wired conductive wires in a one-to-one correspondence.
Further, the second bonding pads and the leads of the lead frame are respectively electrically connected to one another by wire bonding.
As another example of the multichip package using the lead frame, there has been known a multichip package including a plurality of bare chips stacked on at least one of opposed first and second main surfaces of a substrate, a spacer disposed between the two bare chips of these bare chips, which are positioned adjacent to each other vertically, and inner leads which are disposed on both sides in the horizontal direction with the substrate interposed therebetween and connected to their corresponding pads of each bare chip by bonding wires (refer to a patent document 2 (Japanese Laid-open Patent Application No. 2006-294795)).
In the present multichip package, the bonding wires which connect the pads of the bare chip on one end side of the spacer to their corresponding inner leads are disposed so as not to contact the bare chip on the other end side of the same spacer.
The conventional package referred to above always requires higher performance, higher functionality and higher-density packaging.
In the conventional multichip package having the above-described configuration, the mounting of the substrate onto the die pad is performed by ensuring a closed circular bonding or adhesion area having a width of about 2 mm at a peripheral end edge of a substrate mounting area of the die pad, applying an arbitrary and suitable adhesive or bonding material known to date to the bonding area and bonding them to each other.
A multichip package in which a storage type semiconductor chip like, for example, a flash memory chip is sealed in plural form, has been disclosed in the patent document 2 referred to above.
There are often instances where a further increase in capacity is required for the multichip package with the storage type semiconductor chips encapsulated therein in particular.
In such a case, the outer size of each sealed semiconductor chip is often made larger. In order to accommodate such an upsized semiconductor chip, there is a need to realize a further increase in the capacity of the multichip package. There is a case in which there is a need to cause a package size to remain unchanged upon the increase in the capacity of the multichip package.
In order to realize such a need with respect to the configuration disclosed by the patent document 1, for example, there is a need to expand the exclusively-possessed area of each opening at the die pad greater.
When, however, one attempts to make the exclusively-possessed area of the opening greater at the die pad's configuration disclosed in the patent document 1, the following problems might occur.
That is, it is difficult to ensure a bonding or adhesion area required to bond the die pad and the substrate to each other at the die pad. Since the strength of junction between the die pad and the substrate mounted thereto falls short as a result thereof, there is a fear that the reliability of the package is impaired.
In order to ensure the adhesion area, there is a need to make the exclusively-possessed area of the entire die pad greater. As a result, the volume of a sealing portion must be more increased. That is, a further increase in the size of the entire package is unavoidable in this case.
Further, since the strength of the die pad per se falls short when the exclusively-possessed area of each opening is enlarged without expanding the flat or planar size of the die pad, there is a fear that distortion and deformation occur in the lead frame at a package manufacturing process in particular. As a result, unexpected deformation occurs in, for example, a form of bonding between the die pad and the substrate, a form of bonding between each semiconductor chip and the substrate and the connection of each bonding wire. Hence, there is a fear that factors for the reliability of the package, such as the strength of the package and its electric characteristics are impaired.